W29GL128CH9T

品牌；WINBOND 华邦

型号：W29GL128CH9T

封装：TSSOP56

包装：96PCS

数量：19200PCS

年份：12+

WINBOND 大陆代理商。

亿威盛世科技有限公司

联系人：徐波

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W29GL128CH9TWinbond ElectronicsIC FLASH 128MBIT 90NS 56TSOP54 - 立即发货 管件-闪存FLASH128M（16M x 8，8M x 16）90ns并联2.7 V ~ 3.6 V-40°C ~ 85°C56-TFSOP（0.724"，18.40mm 宽）56-TSOP

W29GL128CH9T-ND

现有数量 库存现货 : 540000

可立即发货

制造商

Winbond Electronics

制造商零件编号

W29GL128CH9T

描述IC FLASH 128MBIT 90NS 56TSOP

对无铅要求的达标情况 / 对限制有害物质指令（RoHS）规范的达标情况无铅 / 符合限制有害物质指令（RoHS）规范要求

数据列表W29GL128C

产品相片56-TSOP

标准包装96

类别集成电路 （IC）

家庭存储器

系列-

包装管件

格式 - 存储器闪存

存储器类型FLASH

存储容量128M（16M x 8，8M x 16）

速度90ns

接口并联

电压 - 电源2.7 V ~ 3.6 V

工作温度-40°C ~ 85°C

封装/外壳56-TFSOP（0.724"，18.40mm 宽）

供应商器件封装56-TSOP

W29GL128C

128M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

Publication Release Date: August 2010 Preliminary Revision

BLANK

W29GL128C

Table Contents

GENERAL DESCRIPTION FEATURES CONFIGURATIONS. BLOCK DIAGRAM DESCRIPTION. ARRAY ARCHITECTURE. Sector Address Table FUNCTIONAL DESCRIPTION. Device Operation Instruction Definitions.

7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 7.2.19 7.2.20 7.2.21 7.2.22 7.2.23 Reading Array Data Page Mode Read.5 Device Reset Operation Standby Mode Output Disable Mode.6 Write Operation Byte/Word Selection Automatic Programming Memory Array.7 Erasing Memory Array Erase Suspend/Resume.9 Sector Erase Resume Program Suspend/Resume Program Resume Write Buffer Programming Operation Buffer Write Abort Accelerated Programming Operation Automatic Select Operation.11 Automatic Select Operations Automatic Select Instruction Sequence Enhanced Variable （EVIO） Control Hardware Data Protection Options Inherent Data Protection.13 Power Supply Decoupling.13 Lock Register.15 Individual （Non-Volatile） Protection Mode Factory Locked: Security Sector Programmed Protected factory Customer Lockable: Security Sector Programmed Protected.19

Enhanced Sector Protect/Un-protect

7.3.1 7.3.2

Security Sector Flash Memory Region

7.4.1 7.4.2

Instruction Definition Tables Common Flash Memory Interface （CFI） Mode

7.6.1 Query Instruction Common Flash memory Interface （CFI） Mode

Publication Release Date: August 2010 Preliminary Revision

W29GL128C

ELECTRICAL CHARACTERISTICS Absolute Maximum Stress Ratings. Operating Temperature Voltage Characteristics Switching Test Circuits.

8.4.1 Switching Test Waveform Instruction Write Operation Read Reset Operation.33 Erase/Program Operation.35 Write Operation Status WORD/BYTE CONFIGURATION （#BYTE） DEEP POWER DOWN MODE WRITE BUFFER PROGRAM Device Power-up.51

Characteristics

8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7

Recommended Operating Conditions.

8.6.1Erase Programming Performance Data Retention Latch-up Characteristics 8.10 Capacitance. PACKAGE DIMENSIONS TSOP 56-pin 14x20mm Low-Profile Fine-Pitch Ball Grid Array, 64-ball 11x13mm （LFBA64）. ORDERING INFORMATION. 10.1 Ordering Part Number Definitions. 10.2 Valid Part Numbers Side Marking HISTORY Figure LFBGA64 VIEW FACE DOWN 56-PIN STANDARD TSOP （TOP VIEW） Figure Figure Block Diagram. Figure Enhanced Sector Protect/Un-protect Program Algorithm Figure Lock Register Program Algorithm. Figure Program Algorithm Figure Maximum Negative Overshoot Figure Maximum Positive Overshoot Figure Switch Test Circuit Figure Switching Test Waveform Figure Instruction Write Operation Waveform. Figure Read Timing Waveform Figure #RESET Timing Waveform. Figure Automatic Chip Erase Timing Waveform. Figure Automatic Chip Erase Algorithm Flowchart Figure 8-10 Automatic Sector Erase Timing Waveform. Figure 8-11 Automatic Sector Erase Algorithm Flowchart Figure 8-12 Erase Suspend/Resume Flowchart Figure 8-13 Automatic Program Timing Waveform. Figure 8-14 Accelerated Program Timing Waveform. Figure 8-15 Controlled Write Timing Waveform. Figure 8-16 Automatic Programming Algorithm Flowchart

W29GL128C

Figure 8-17 Figure 8-18 Figure 8-19 Figure 8-20 Figure 8-21 Figure 8-22 Figure 8-23 Figure 8-24 Figure 8-25 Figure 8-26 Figure 8-27 Figure Figure Figure 10-1 Table Table Table Table Table Table Table Table Table Table Table Table 7-10 Table 7-11 Table 7-12 Table 7-13 Table 7-14 Table 7-15 Table 7-16 Table 7-17 Table 7-18 Table 7-19 Table 7-20 Table 7-21 Table 7-22 Table Table Table Table Table Table Table Table Table Table 8-10 Table 8-11 Table 8-12 Table 8-13 Table 10-1 Table 11-1 Silicon Read Timing Waveform. Data# Polling Timing Waveform （During Automatic Algorithms） Status Polling Word Programming/Erase Status Polling Write Buffer Program Flowchart Toggling Timing Waveform （During Automatic Algorithms） Toggle Algorithm. #BYTE Timing Waveform Read operations Page Read Timing Waveform. Deep Power Down mode Waveform Write Buffer Program Flowchart Timing Device Power-Up TSOP 56-pin 14x20mm LFBGA 64-ball 11x13mm Ordering Part Numbering. Description. Sector Address Device Operation Device Operation （continue）. Polling During Embedded Program Operation Polling During Embedded Sector Erase Operation Polling During Embedded Chip Erase Operation Polling During Embedded Erase Suspend Polling During Embedded Program Suspend. Polling Buffer Write Abort Flag Auto Select MFR/Device ID/Secure Silicon/Sector Protect Read Lock Register Bits Sector Protection Status Table Factory Locked: Security Sector. Reads, Sector Verify, Security Sector Entry/Exit Program, Write Buffer, CFI, Erase Suspend Deep Power Down Lock Register Global Non-Volatile. Functions. Volatile Functions Mode: Data Values Mode: System Interface Data Values Mode: Device Geometry Data Values. mode: Primary Vendor-Specific Extended Query Data Values Absolute Maximum Stress Ratings. Operating Temperature Voltage Characteristics Test Specification. Characteristics Characteristics #RESET RY/#BY Characteristics Word/Byte Configuration （#BYTE）. Characteristics Deep Power Down. Characteristics Device Power Characteristics Erase Programming Performance. Data Retention Latch-up Characteristics Capacitance. Valid Part Numbers Markings Revision History Publication Release Date: August 2010 Preliminary Revision

W29GL128C

GENERAL DESCRIPTION

W29GL128C Parallel Flash memory provides storage solution embedded system applications that require better performance, lower power consumption higher density. device random access speed 90ns fast page access speed 25ns, well significantly faster program erase time than products available market today. W29GL128C also offers special features such Compatible Manufacturer that makes device industry standard compatible without need change firmware.

FEATURES

Compatible manufacturer drop-in replacement firmware change required Faster Erase Program time Erase is1.5x faster than industry standard Program faster than industry standard Allows improved production throughput faster field updates （Common Flash Interface） support Single Read/Program/Erase （2.7 3.6V） Enhanced Variable control input levels （address, control, output levels determined voltage EVIO input. EVIO ranges from 1.65 #WP/ACC Input Accelerates programming time （when applied） greater throughput during system production Protects first last sector regardless sector protection settings Hardware reset input （#reset） resets device Ready/#Busy output （RY/#BY） detects completion program erase cycle Packages 56-pin TSOP 64-ball LFBGA

64k-Word/128k-Byte uniform sector architecture Total uniform sectors 32-Word/64-Byte write buffer Reduces total program time multipleword updates 8-Word/16-Byte page read buffer Secured Silicon Sector area Programmed locked customer during production 128-word/256-byte sector permanent, safe identification using 8-word/16-byte random electronic serial number Enhanced Sector Protect using Dynamic Individual mechanisms Polling/Toggling methods used detect status program erase operation Suspend resume commands used program erase operations More than 100,000 erase/program cycles More than 20-year data retention Software Hardware write protection Write-Protect portion memory Enable/Disable protection with bottom array protection power consumption Deep power down mode Wide temperature range

Publication Release Date: August 2010 Preliminary Revision

W29GL128C

CONFIGURATIONS

BLOCK DIAGRAM

EVIO

EVIO RY/#BY #BYTE #RESET #WP/ACC DQ15/A-1

DQ14

DQ13

#BYTE DQ15/A-1

CONTROL

OUTPUT BUFFER

#RESET

DQ12

DQ10

DQ11

RY/#BY #WP/ACC

EVIO

DQ15/A-1

DECODER

MAIN ARRAY

Figure

LFBGA64 VIEW FACE DOWN

Figure

Block Diagram

DESCRIPTION

SYMBOL NAME A0-A22 Address Inputs DQ0-DQ14 Data Inputs/Outputs DQ15/A-1 Word DQ15 Data mode Input/Output Address Input Byte mode Chip Enable Output Enable Write Enable #WP/ACC Hardware Write Protect/ Acceleration #BYTE Byte Enable Input #RESET Hardware Reset RY/#BY Ready/Busy Status Power Supply EVIO Enhanced Variable Supply Ground Connection Table Description

#RESET #WP/ACC RY/#BY

#BYTE DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10 EVIO

Figure

56-PIN STANDARD TSOP （TOP VIEW）

W29GL128C

ARRAY ARCHITECTURE

Sector Address Table

Sector Address Sector Size A22-A16 （KByte/KWord） 0000000 128/64 0000001 128/64 1111110 128/64 1111111 128/64 Sector Address Start Finish 000000h 01FFFFh 020000h 03FFFFh FC0000h FDFFFFh FE0000h FFFFFFh Start Finish 000000h 00FFFFh 010000h 01FFFFh 7E0000h 7EFFFFh 7F0000h 7FFFFFh

Sector SA00 SA01 SA126 SA127 Table

Note: address range [A22:A-1] byte mode （#BYTE VIL） [A22:A0] word mode （#BYTE VIH）

Publication Release Date: August 2010 Preliminary Revision

W29GL128C

FUNCTIONAL DESCRIPTION

Device Operation

Address（4） Data DQ[7:0] High-Z High-Z High-Z DOUT #BYTE #WP/ACC Data DQ[15:8] HighHigh-Z HighHigh-Z HighHigh-Z DOUT DQ[14:8]=HighDIN Note（1,2） DQ15=A-1

Mode Select #Reset

Device Reset

Standby VCC±0.3V VCC±0.3V Mode Output Disable Read Mode Write Accelerated Program Table Device Operation

Notes:

first last sector protected #WP/ACC=VIL. When #WP/ACC VIH, protection conditions outmost sector depends previous protection conditions. Refer enhanced protect feature. DQ[15:0] input （DIN） output （DOUT） pins according requests instruction sequence, sector protection, data polling algorithm. Word Mode （Byte#=VIH）, addresses Byte Mode （Byte#=VIL）, addresses （DQ15）,.

Description Read Silicon Manufacturer Code Device Cycle Cycle Cycle

Control Inputs

DQ[7:0] 01/00

DQ[15:8] BYTE WORD

Sector Lock Status Verification（1） Secure Sector Secure Sector Table Device Operation （continue）

Notes:

99/19 89/09

Sector unprotected code:00h. Sector protected code:01h. Factory locked code: protects high address sector: 99h. protects address sector: Factory unlocked code: protects high address sector: 19h. protects address sector:W29GL128C

Instruction Definitions

device operation initiated writing specific address data commands sequences into instruction register. device will reset reading array data when writing incorrect address data values writing them improper sequence. addresses will latched falling edge #CE, whichever happens later; while data will latched rising edge #CE, whichever happens first. Please refer timing waveforms. 7.2.1 Reading Array Data default state after power reset operation Read mode. execute read operation, chip enabled setting active high. same time, required address status register location provided address lines. system reads addressed location contents Data pins after timing requirements have been met. Output data will accessible Data pins either device it＇s outputs enabled being High, outputs will remain tristate condition. When device completes embedded memory operation （i.e., Program, automatic Chip Erase Sector Erase） successfully, will return Read mode from address memory array data read. However, embedded operation fails complete, verifying status register （exceeds time limit flag） going high during operations, this time system should execute Reset operation causing device return Read mode. Some operating states require reset operation return Read mode such Time-out condition during program erase failed condition, indicated status register going High during operation. Failure during either these states will prevent device from automatically returning Read mode. During device Auto Select mode mode, reset operation required terminate their operation.

above situations, device will return Read mode unless reset operation executed （either hardware reset software reset instruction） system will able read array data. device will enter Erase-Suspended Read mode device receives Erase Suspend instruction while Sector Erase state. erase operation will pause （after time delay exceeding 20µs） prior entering Erase-Suspend Read mode. this time data programmed read from sector that being erased. Another verify device status read addresses inside sectors being erased. This will only provide contents status register. Program operation during Erase-Suspend Read mode valid sector（s） will automatically return Erase-Suspend Read mode upon successful completion program operation. Erase Resume instruction must executed exit Erase-Suspended Read mode, which time suspended erase operations will resume. Erase operation will resume where left continue until successful completion unless another Erase Suspend instruction received. 7.2.2 Page Mode Read Page Mode Read page sizes bytes words. higher addresses A[22:3] accesses desired page. access particular word byte page, selected A[2:0] word mode A[2:0,A-1] byte mode. Page mode turned keeping "page-read address" constant changing "intra-read page" addresses. page access time tCE, followed page read time. When toggles, access time tCE. Publication Release Date: August 2010 Preliminary Revision

W29GL128C

7.2.3 Device Reset Operation

Pulling #RESET period equal greater than will return device Read mode. device performing program erase operation, reset operation will take most period tREADY1 before device returns Read mode. RY/#BY will remain （Busy Status） until device returns Read mode. Note, device draws larger current #RESET held voltages greater that GND+0.3V less than equal VIL. When #RESET held GND±0.3V, device only consumes Reset （ICC5） current. recommended system reset signal #RESET flash memory. This allows device reset with system puts state where system immediately begin reading boot code from Executing Reset instruction will reset device back Read mode following situations: During erase instruction sequence, before full instruction completed. Sector erase time-out period Erase failed, while High. During program instruction sequence, before full instruction completed, including erase-suspended program instruction. Program failed, while High well erase-suspended program failure. Auto-ｓelect mode mode user must issue reset instruction reset device back Read mode when device Auto-Select mode mode, when there program erase failure （DQ5 High）. When device performing Programming （not program fail） Erasing （Not erase fail） function, device will ignore reset commands. Standby Mode

7.2.4

Standby mode entered when both #RESET driven ±300mV （inactive state）. this time output pins placed high impedance state regardless state pins device will draw minimal standby current （ICC4）. device deselected during erase program operation, device will draw active current until operation completed. 7.2.5 Output Disable Mode controls state Data pins. driven High （VIH）, Data pins will remain high impedance driven Low, Data pins will drive data affect RY/BY# output pin）. 7.2.6 Write Operation execute write operation, Chip Enable （#CE） driven Output Enable （#OE） pulled high disable Data pins high impedance state. desired address data should present appropriate pins. Addresses latched falling edge either Data latched rising edge either #WE. example, please refer timing diagrams Figure Figure 8-15. invalid write instruction, defined this datasheet written device, device undefined state.

W29GL128C

7.2.7 Byte/Word Selection

choose between Byte Word mode, #BYTE input used ｓelect data input/output Data pins organization array data. #BYTE driven High, Word mode will selected Data pins will active. #BYTE pulled Low, Byte mode will active only Data DQ[7:0] will active. remaining Data pins （DQ[14:8]） will high impedance state DQ15 becomes address input pin. 7.2.8 Automatic Programming Memory Array program memory array Byte Word mode, refer Instruction Definition Tables correct cycle defined instructions that include unlocking instruction cycles, program cycle instruction subsequent cycles containing specified address location byte word desired data content, followed start embedded algorithm automatically program array. Once program instruction sequence been executed, internal state machine commences execution algorithms timing necessary programming cell verification. Included this operation generating suitable program pulses, checking cell threshold voltage （VT） margins, cells pass verification have acceptable margins, repetitive program pulse sequence will cycled again. internal process mechanisms will protect cells that pass margin verification tests from being over-programmed prohibiting further program pulses passing cells failing cells continue through internal programming sequence until pass. This feature allows user only perform auto-programming sequence once device state machine takes care program verification process. Array bits during programming only change status （erase state） （programmed state）. possible reverse with programming operation. This only done first performing erase operation. Keep mind, internal write verification only checks detects errors cases where successfully programmed "0". During embedded programming algorithm process commands written device will ignored, except hardware reset program suspend instruction. Hardware reset will terminate program operation after period time, exceed 10µs. case Program Suspend executed, device will enter program suspend read mode. When embedded program algorithm completed program terminated hardware reset, device will return Read mode. user check completion reading following bits status register, once embedded program operation started: Status progress DQ7# Toggling Exceeded time DQ7# Toggling limit Table Polling During Embedded Program Operation

Note:

RY/#BY1

RY/#BY open drain output should connected through high value pull-up resistor.

Publication Release Date: August 2010 Preliminary Revision

W29GL128C

7.2.9 Erasing Memory Array

Sector Erase Chip Erase possible types erase operations executed memory array. Sector Erase operation erases more selected sectors this simultaneous. Chip Erase operation erases entire memory array, except protected sectors.

7.2.9.1 Sector Erase

sector erase operation returns selected sectors memory state, effectively clearing data. This action requires instruction cycles commence erase operation. unlock sequence first cycles, followed configuration cycle, fourth fifth also "unlock cycles", Sector Erase instruction sixth cycle. internal 50µs time-out counter started once sector erase instruction sequence been completed. During this time, additional sector addresses Sector Erase commands issued, thus allowing multiple sectors selected erased simultaneously. Once 50µs time-out counter reached limit, additional command instructions will accepted embedded sector erase algorithm will commence. Note, that 50µs time-out counter restarts after every sector erase instruction sequence. device will abort return Read mode, instruction other than Sector Erase Erase Suspend attempted during time-out period. Once embedded sector erase algorithm begins, instructions except Erase Suspend Hardware Reset will ignored. hardware reset will abort erase operation return device Read mode. embedded sector erase algorithm status verified following: Status DQ31 Time-out period Toggling progress Toggling Exceeded time limit Toggling Table Polling During Embedded Sector Erase Operation

Note:

Toggling Toggling Toggling

RY/#BY2

status 50µs time-out indicator. When DQ3=0, 50µs time-out counter reached zero Sector Erase instruction maybe issued specify address another sector erased. When DQ3=1, 50µs time-out counter expired Sector Erase operation already begun. Erase Suspend only valid instruction that maybe issued once embedded erase operation underway. RY/#BY open drain output should connected through high value pull-up resistor. When attempt made erase only protected sector（s）, erase operation will abort thus preventing data changes protected sector（s）. will output will toggle briefly （100µs less） before aborting returning device Read mode. unprotected sectors also specified, however, they will erased normally protected sector（s） will remain unchanged. localized indicator showing specified sector undergoing erase operation not. toggles when user reads addresses where sectors actively being erased erase mode） erased erase suspend mode）.

W29GL128C

7.2.9.2 Chip Erase

Chip Erase operation returns memory locations containing state state, effectively clearing data. This action requires instruction cycles commence erase operation. unlock sequence first cycles, followed configuration cycle, fourth fifth also "unlock cycles", sixth cycle initiates chip erase operation. Once chip erase algorithm begins, other instruction will accepted. However, hardware reset executed operating voltage below acceptable levels, chip erase operation will terminated automatically returns Read mode. embedded chip erase algorithm status verified following: Status progress Toggling Exceeded time limit Toggling Table Polling During Embedded Chip Erase Operation

Note:

Toggling Toggling

RY/#BY1

RY/#BY open drain should connected through high value pull-up resistor.

7.2.10

Erase Suspend/Resume

there sector erase operation progress, Erase Suspend instruction only valid instruction that issued. Once Erase Suspend instruction executed during 50µs timeout period following Sector Erase instruction, time-out period will terminate right away device will enter Erase-Suspend Read mode. Erase Suspend instruction executed after sector erase operation started, device will enter Erase-Suspended Read mode until approximately 20µs （5µs typical） time elapsed. determine device entered EraseSuspend Read mode, DQ6, RY/#BY status verify state device. Once device entered Erase-Suspended Read mode, possible read program sector（s） except those being erased erase operation. Only contents status register present when attempting read sector that been scheduled erase programmed when suspend mode. resume instruction must executed recommend checking toggle status, before issuing another erase instruction. status register bits verified determine current status device: Status DQ1RY/#BY Erase suspend read erase suspended sector toggle Toggle Erase suspend read non-erase suspended sector Data Data DataData Data Data Erase suspend program non-erase suspended sector DQ7# Toggle Table Polling During Embedded Erase Suspend Instruction sets such read silicon sector protect verify, program, query erase resume also executed during Erase-Suspend mode, except sector chip erase. 7.2.11 Sector Erase Resume Only Erase-Suspended Read mode Sector Erase Resume instruction valid command. Once erase resumes, another Erase Suspend instruction executed, allow 400µs interval between Erase Resume next Erase Suspend instruction.

Publication Release Date: August 2010 Preliminary Revision

W29GL128C

7.2.12 Program Suspend/Resume Once program operation progress, Program Suspend only valid instruction that maybe executed. Verifying device entered Program-Suspend Read mode after executing Program-Suspend instruction, done checking RY/#BY DQ6. Programming should halt within 15µs maximum （5µs typical）. sector（s） read except those being program suspended. Trying read sector being program suspended invalid. Before another program operation executed, Resume instruction must performed toggling status verified. status register bits shown following table determine current state device:

Status RY/#BY Program suspend read program suspended sector Program suspend read non-program suspended sector Data Data Data Data Data Data Table Polling During Embedded Program Suspend Instruction sets such read silicon sector protect verify, program, query also executed during Program/Erase-Suspend mode. 7.2.13 Program Resume program Resume instruction valid only when device Program-Suspended mode. Once program resumes, another Program Suspend instruction executed. Insure there least interval between Program Resume next Suspend instruction. 7.2.14 Write Buffer Programming Operation Write Buffer Programming Operation, programs 64bytes 32words step programming operation. begin execution Write Buffer Programming, start with first unlock cycles, third cycle writes programming Sector Address destination followed Write Buffer Load Instruction （25h）. fourth cycle repeats Sector Address, while write data number intended word locations written minus one. （Example, number word locations written then value would 8h.） cycle first starting address/data set. This will first pair programmed consequentially, sets "write-buffer-page" address. Repeat Cycle format each additional address/data sets written buffer. Keep mind sets must remain within write buffer page address range. not, operation will ABORT. "write-buffer-page" selected choosing address A[22:5]. second step will program contents write buffer page. This done with cycle, containing sector address that used step "Write Buffer Program Confirm" instruction （29h）. Standard suspend/resume commands used during operation write-buffer. Also, once write buffer programming operation finished, it＇ll return normal READ mode. Write buffer programming conducted sequence. However functions, autoselect, Secured Silicon sector functional when program operation progress. Multiple write buffer programming operations same write buffer address range without intervention erase accessible. write buffer address range cannot programmed from back

W29GL128C

7.2.15 Buffer Write Abort Write Buffer Programming Sequence will ABORT, following condition takes place: word ｃount minus loaded bigger than page buffer size （32） during, "Number Locations Program." Sector Address written same specified during Write-Buffer-Load instruction. Address/Data inside Write Buffer Page range which during cycle first initial write-buffer-page ｓelect address/data set. "Program Confirm Instruction" after assigned number "data load" cycles.

After Write Buffer Abort, status register will DQ1=1, DATA# （last address loaded）, DQ6=toggle, DQ5=0. This status represents Write Buffer Programming Operation ABORTED. Write-to-Buffer-Abort Reset instruction sequence written reset device back read array mode. Buffer Write Abort. When DQ1=1, device will abort from buffer write operation back read status register shown following table: Status Buffer Write Busy DQ7# Toggle Buffer Write Abort DQ7# Toggle Buffer Write Exceeded Time Limit DQ7# Toggle Table Polling Buffer Write Abort Flag 7.2.16 Accelerated Programming Operation device will enter Accelerated Programming mode applying high voltage （VHH） #WP/ACC pin. Accelerated Programming mode allows system skip normal unlock sequences instruction program byte/word locations directly. current drawn from #WP/ACC during accelerated programming more that IACC1. Important Note: exceed accelerated programs sector. 7.2.17 Automatic Select Operation There basically methods access Automatic Selection Operations; Automatic Select Instructions through software commands High Voltage applied Automatic Select Instruction Sequence later this section details equivalent instruction operations that require VHH. following five operations require raised VHH.

7.2.17.1 Sector Lock Status Verification

RY/#BY

verify protected state sector using operations, execute Read Operation with applied sector address present address pins A[22:12], address pins held Low, address pins held High. Low, sector considered protected, High, sector considered protected.

7.2.17.2 Read Silicon Manufacturer Code

Winbond＇s 29GL family Parallel Flash memories feature Industry Standard compatible Manufacturer code 01h. verify Silicon Manufacturer code, execute Read Operation with applied address pins held Low. code then read data bits DQ[7:0].

Publication Release Date: August 2010 Preliminary Revision

W29GL128C

7.2.17.3 Read Silicon Device Code

verify Silicon Device Codes, execute Read Operation with applied address pins have several combinations return Winbond Device codes 7Eh, 01h, which shown data bits DQ[7:0]. Table 7-2.

7.2.17.4 Read Indicator Security Sector High Address

verify that Security Sector been factory locked, execute Read Operation with applied address pins held Low, address pins held High. Security Sector been factory locked, code 99h（Highest Address Sector） 89h（Lowest Address Sector） will shown data bits DQ[7:0]. Otherwise, factory unlocked code 19h（H）/09（L） will shown. 7.2.18 Automatic Select Operations Automatic Select instruction show Table 7-13 executed device following modes; Read, Program Suspended, Erase-Suspended Read, CFI. which time user issue （two unlock cycles followed Automatic Select instruction 90h） enter Automatic Select mode. Once Automatic Select mode, user query Manufacturer Device Security Sector locked status, Sector protected status multiple times without executing unlock cycles Automatic Select instruction （90h） again. Once Automatic Select mode, executing Reset instruction （F0h） will return device back valid mode from which left when Automatic Select mode first executed. Another previously mentioned enter Automatic Select mode operation shown Table Device Operation. Once high voltage （VHH） removed from pin, device will return back valid mode from which left when Automatic Select mode first executed. 7.2.19 Automatic Select Instruction Sequence Accessing manufacturer device verifying whether secured silicon locked whether sector protected purpose Automatic Select mode. There four instruction cycles that comprise Automatic Select mode. first cycles write unlock commands, followed Automatic Select instruction （90h）. fourth cycle read cycle, user read address number times without entering another instruction sequence. exit Automatic Select mode back read array, Reset instruction necessary. other instructions allowed except Reset Instruction once Automatic Select mode been selected. Refer following table more detailed information. Data （hex） Representation 227E/2221/2201 7E/21/01 99/19（H） Word Factory locked/unlocked 89//09（L） Secure Silicon 99/19（H） Byte Factory locked/unlocked 89/09（L） Word （Sector address） 00/01 Unprotected/protected Sector Protect Verify Byte Sector address） 00/01 Unprotected/protected Table Auto Select MFR/Device ID/Secure Silicon/Sector Protect Read Word Manufacturer Byte Word Device W29GL128C Byte Address X01/0E/0F X02/1C/1E

W29GL128C

7.2.20 Enhanced Variable （EVIO） Control

Enhanced Variable （EVIO） control allows host system voltage levels that device generates tolerates inputs outputs （address, control, signals）. EVIO range 1.65 VCC. example, EVIO 1.65-3.6 volts allows volt levels, driving receiving signals from other devices same data bus. 7.2.21 Hardware Data Protection Options Hardware Data Protection second main sector protections offered W29GL128.

7.2.21.1 #WP/ACC Option

setting #WP/ACC VIL, highest lowest sector （device specific） protected from erase/program operations. #WP/ACC High, highest Lowest sector revert back previous protected/unprotected state. Note: input load current increase, #WP/ACC when device into standby mode.

7.2.21.2 Write Protect

This device will accept write instructions when less that VWPT （VCC Write Protect Threshold）. This prevents data from inadvertently being altered during power-up, power-down, temporary power loss level VCC. lower that VWPT, device automatically resets itself will ignore write cycles until greater than VWPT. Once rises above VWPT, insure that proper signals control pins avoid unexpected program erase operations.

7.2.21.3 Write Pulse "Glitch" Protection

Pulses less than viewed glitches control signals #CE, #WE, will considered valid write cycles.

7.2.21.4 Power-up Write Inhibit

device ignores first instruction rising edge #WE, upon powering device, VIH.

7.2.21.5 Logical Inhibit

write cycle ignored when either VIH, VIH, VIL. valid write cycle requires both with VIH. 7.2.22 Inherent Data Protection device built-in mechanism will reset Read mode during power avoid accidental erasure programming.

7.2.22.1 Instruction Completion

Invalid instruction sets will result memory returning read mode. Only upon successful completion valid instruction will device begin erase program operation.

7.2.22.2 Power-up Sequence

device placed Read mode, during power-up sequence. 7.2.23 Power Supply Decoupling reduce noise effects, 0.1µF capacitor recommended connected between GND.

Publication Release Date: August 2010 Preliminary Revision

W29GL128C

Enhanced Sector Protect/Un-protect

This device from factory Individual Protection mode Enhanced Sector Protect scheme. user disable enable programming erasing operation individual sector whole chip. figure below helps describe overview these methods. device defaults Individual mode sectors unprotected when shipped from factory. following flow chart shows detailed algorithm Enhanced Sector Protect:

Start

Individual Protection Mode （Default）

Lock

IPB=0

lock locked changeable

IPB=1

Lock Unlocked Changeable

Dynamic Write Protect （DPB） DPB=0 Sector Protect DPB=1 Sector Unprotect

Sector Array

Individual Protect （IPB） IPB=0 Sector Protect IPB=1 Sector Unprotect

Figure

Enhanced Sector Protect/Un-protect Program Algorithm

W29GL128C

7.3.1 Lock Register

User choose Secured Silicon Sector Protection security sector protection method setting Lock Register bit, DQ0. Lock Register 16-bit time programmable register. Once programmed DQ0, will locked that mode permanently. Once Instruction Entry instruction sequence Lock Register Bits issued, sectors read write functions disabled until Lock Register Exit sequence been executed. memory sectors extended memory sector protection configured using Lock Register. DQ[15:1] Don＇t Care Lock Register Bits

Start

Secured Silicon Sector Protection

Table 7-10

Write Data AAh, Address 555h

Write Data 55h, Address2AAh

Lock Register instruction entry

Write Data 40h, Address 555h

Write Data A0h, Address don＇t care Lock Register data program Write Program Data, Address don＇t care

Data Polling Algorithm

Done Pass DQ5=1 Fail

Exit lock Register instruction

Reset instruction

Figure

Lock Register Program Algorithm

Publication Release Date: August 2010 Preliminary Revision

W29GL128C

7.3.2

7.3.2.1

Individual （Non-Volatile） Protection Mode

Individual Protection Bits （IPB）

Individual Protection （IPB） nonvolatile bit, sector, with endurance equal that Flash memory array. Before erasing, preprogramming verification managed device, monitoring necessary. Individual Protection Bits sector sector program instruction. Once "0", linked sector protected, blocking program and/or erase functions that sector. cannot erased individually, executing "All Erase" instruction will erase simultaneously. Read write functions disabled when programming going sectors until this mode exits. case protected sectors need unprotected, first, Lock must performing following: power-cycle device perform hardware reset. Second, "All Erase instruction needs performed. Third, Individual Protection Bits need once again reflect desired settings finally, Lock needs once again which locks Individual Protection Bits device functions normally once again. Executing Read instruction device required verify programming state given sector. Refer Program Algorithm flow chart below details. Note that While Lock set, Program and/or erase instructions will executed times without programming and/or erasing IPB. best protection results, recommended execute Lock instruction early boot code. Also, protect boot code holding WP#/ACC VIL. Note that bits perform same when WP#/ACC VHH, when WP#/ACC =VIH. While command mode, read within that sector will bring status back that sector. Read must executed read mode. Issuing Instruction Exit will reset device normal read mode enabling reads writes array.

Dynamic Protection Bits （DPB）